The present invention relates to a bit synchronization circuit for synchronizing an input signal of an arbitrary phase with a clock of a fixed clock rate.
The speech path equipment of a telephone exchange system is equipped with a bit synchronization circuit for each subscriber's line for switching after phasing input data of different phases differing with subscriber's lines.
Broad-band integrated service digital network (ISDN) service has been developed progressively in recent years and efforts have been made for the standardization of communication equipments capable of transmitting signals at a high subscriber's line data signaling rate on the order of 150 Mb/sec.
In a telephone exchange system for dealing with signal transmission at such a high data signaling rate, waveform distortion resulting from phase jitter that occurs when data passes cables, connectors or switches, and the variation of duty cycle has great influence on the performance of the telephone exchange system because the pulse width of the signal is small, and increase in the number and scale of switches enhances the waveform distortion, which makes the reproduction of signals impossible.
Accordingly, the data must be regenerated every time the data passes a switch to correct waveform distortion. A bit synchronization circuit is used as means for regenerating data.
The bit synchronization circuit phases input data by synchronizing the input data of an arbitrary phase with a clock of a fixed clock rate, for example, 150 MHz, for signal regeneration. Accordingly, the waveform distortion, such as jitter, of the input data can be corrected by regenerating the input data by the bit synchronization circuit.
In regenerating input data by such a bit synchronization circuit using a clock of a fixed clock rate, the change point of the clock must be synchronized with the center of one period of the input data, since the waveform of the periphery of each period of the input data is distorted and the change point is unstable.
A bit synchronization circuit of such a kind is disclosed in D. Boettle & M. Klein, "High Speed (140 Mb/sec) Switching Techniques for Broad-band Communications", Proceedings of International Zurich Seminar on Digital Communications 1986, C4.1-C4.4, pp. 97-100, FIG. 6. This known bit synchronization circuit delays input data by a fixed time, compares the phases of the delayed input data and a clock, and controls the delay of the input data so that the change point of the clock coincides with the center of the input data. The bit synchronization circuit is provided with a plurality of retardation elements for delaying the input data, and a control circuit for controlling the delay time.
The telephone exchange system must be provided with a bit synchronization circuit for each subscriber's line. Accordingly, it is desirable to employ a LSI as a bit synchronization circuit to construct a large-scale telephone exchange system.
However, it has been difficult to construct the aforesaid known bit synchronization circuit, because the bit synchronization circuit needs to be provided with many retardation elements taking into consideration difference in propagation delay time between the retardation elements, and the delay time control circuit is complicated. Furthermore, the control circuit and the phase difference detecting circuit of the bit synchronization circuit are complicated, and hence a comparatively long time is required for synchronizing the change point of the clock with the center of the input data after the detection of the phase difference. Furthermore, step-out occurs immediately when the input data includes noise, and the margin of operation for covering the fluctuation of the input data is small.